Design of a reconfigurable multi-core architecture for streaming applications with a case study on performance evaluation of FIR-filters

This paper presents a reconfigurable multi-core architecture which is composed of nine nodes connected to each other in a mesh topology network. The central node hosts a general purpose processor and serves as the system controller and the surrounding nodes are equipped with coarse grain reconfigurable arrays that provide hardware flexibility and parallelism. This architecture is mainly targeted for streaming applications. As a case study, performance and hardware usage for implementations of FIR filters with different number of taps are presented. Each implementation was prototyped on an Altera FPGA and to ensure the correctness of the system, RTL simulations were carried out. The performance results were compared with the same applications implemented on a single-core processor. The timing analyses show speed-ups up to 3.6x.