DocumentCode
634647
Title
Error-tolerance evaluation and design techniques for motion estimation computing arrays
Author
Shyue-Kung Lu ; Ming-Chang Chen ; Yen-Chi Chen
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
fYear
2013
fDate
8-10 July 2013
Firstpage
167
Lastpage
168
Abstract
In this paper, we propose evaluation flow for estimating the performance degradation of motion estimation (ME) architectures when faults occur and decide their acceptability. Moreover, when a fault is evaluated as unacceptable, a swap-based error-tolerance (ET) technique is proposed to increase the acceptability of this fault. According to experimental results, the acceptability and effective yield can be improved significantly with negligible hardware overhead.
Keywords
motion estimation; parallel processing; performance evaluation; ET; ME; design techniques; error-tolerance evaluation; evaluation flow; motion estimation architectures; motion estimation computing arrays; performance degradation; swap-based error-tolerance technique; Circuit faults; Computer architecture; Fault diagnosis; Hardware; Motion estimation; PSNR; Video sequences; PSNR; error tolerance; motion estimation; yield;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International
Conference_Location
Chania
Type
conf
DOI
10.1109/IOLTS.2013.6604070
Filename
6604070
Link To Document