Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs

This paper addresses the high-performance systems which are based on swapping relocatable partial bitstreams (also called hardware tasks) in and out of an FPGA device using Dynamic Partial Reconfiguration (DPR) in Xilinx Virtex FPGAs. Configuration speed is important in such systems to achieve high performance. Previous research efforts were focused on over-clocking the Internal Configuration Access Port (ICAP) and compressing the partial bitstreams of the hardware tasks to enhance the configuration speed. We propose the use of the Multiple Frame Write (MFW) feature to significantly reduce the configuration time when multiple instances of a hardware task are needed. In this paper, we demonstrate the design and implementation of a novel internal reconfiguration engine which dynamically generates partial bitstreams required for simultaneous configuration of multiple clones of relocatable hardware tasks.