Simulation and implementation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron

Author

Inoue, Ken ; Takeuchi, N. ; Yamanashi, Y. ; Yoshikawa, N.

Author_Institution

Dept. of Electr. & Comput. Eng., Yokohama Nat. Univ., Yokohama, Japan

fYear

2013

fDate

7-11 July 2013

Firstpage

1

Lastpage

3

Abstract

We have been studying ultra-low-power logic circuits using adiabatic quantum-flux-parametron (AQFP) logic, whose power consumption can be decreased significantly by changing their potential energies adiabatically using AC exciting currents. In this study, we designed an 8-bit carry look-ahead adder (CLA) using an AQFP cell library based on the AIST Nb 2.5 kA/cm² standard process (STP2) and evaluated its circuit properties. The CLA is composed of 1224 critically-dumped 50-μA Josephson junctions, which occupy the area of 1.74 × 0.99 mm². Simulation results show that the CLA has a wide bias margin of ±29.5%, and the energy dissipation is 16.4 aJ per clock cycle at 5-GHz operation.

Keywords

adders; carry logic; low-power electronics; microwave parametric oscillators; superconducting logic circuits; AC exciting currents; AIST Nb standard process; AQFP cell library; AQFP logic; CLA; Josephson junctions; adiabatic quantum-flux-parametron logic; carry look-ahead adder; circuit properties; current 50 muA; energy dissipation; frequency 5 GHz; power consumption; ultralow-power logic circuits; word length 8 bit; Adders; Clocks; Energy dissipation; Energy efficiency; Josephson junctions; Junctions; Logic gates; Kogge-Stone adder; QFP; adiabatic circuits; carry look-ahead adder; low energy; superconducting devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International

Conference_Location

Cambridge, MA

Print_ISBN

978-1-4673-6369-3

Type

conf

DOI

10.1109/ISEC.2013.6604271

Filename

6604271