Application Specific Low Leakage data Cache for embedded processors

Previous studies have suggested using drowsy caches to reduce leakage power in caches. Such studies often move an entire cache line in and out of the drowsy mode to reduce leakage power while maintaining performance. In this work we extend previous work and introduce Application Specific Low Leakage Cache (ASL) as an alternative power-aware data cache for embedded processors. ASL builds on the observation that often only one or two words of a cache line are accessed during long periods. Accordingly, we investigate a word-size granularity approach to drowsy caches. We introduce two ASL variations, i.e., B-ASL and P-ASL. In B-ASL we move all words in a cache line into the drowsy (low leakage) mode and wakeup only the words accessed. In P-ASL we make sure recently accessed words stay in the non-drowsy (high leakage) mode to maintain performance. We show that ASL can reduce leakage power in caches by 88% while paying an average performance cost of 0.7% compared to drowsy cache..