Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator

Author

Jaehyeok Yang ; Joon-Yeong Lee ; Sun-Jae Lim ; Hyeon-Min Bae

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

Volume

61

Issue

11

fYear

2014

fDate

Nov. 2014

Firstpage

880

Lastpage

884

Abstract

A phase-rotator-based all-digital phase-locked loop for spread-spectrum clock generation is presented. It combines a dual-tone triangular and a random modulation profile to achieve a balance between electromagnetic interference reduction and broadband jitter generation. The test chip, fabricated using a 90-nm CMOS process, achieves a 43-dB total EMI reduction at the resolution bandwidth of 100 Hz without incurring a notable bit-error-rate penalty at the receiver´s side and consuming only 15.8 mW at 6 GHz from a 1-V supply.

Keywords

CMOS integrated circuits; digital phase locked loops; electromagnetic interference; interference suppression; jitter; signal generators; CMOS process; all-digital phase-locked loop; bandwidth 100 Hz; bit-error-rate penalty; broadband jitter generation; dual-tone triangular; electromagnetic interference reduction; frequency 6 GHz; phase-rotator; power 15.8 mW; random modulation profile; size 90 nm; spread-spectrum clock generator; voltage 1 V; Clocks; Electromagnetic interference; Frequency modulation; Generators; Jitter; Phase locked loops; Electromagnetic interference (EMI); phase rotator; phase-locked loop (PLL); spread-spectrum clock (SSC);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2356893

Filename

6895141