An analog dual delay locked loop using coarse and fine programmable delay elements

In the paper we consider architecture of an analog dual delay locked loop (DLL). It uses an simply-implementable coarse delay line to push the loop close to lock state, and a fine programmable delay line to make small adjustments to the output phase. Both coarse- as well as fine-delay line are implemented as a cascades of variable-delay elements based on single-ended Schmitt triggers. For the correction of a duty cycle of the delayed output signal, particularly in the coarse delay segment, a very effective duty cycle correction (DCC) has been applied. The complete architecture of the DLL utilizing aforementioned building blocks, has also been simulated using Spectre and BSIM3V3 device models for 1.8V 180nm CMOS technology from UMC. Most important simulation results are presented.