CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a reduction of power dissipation and a reduction of overall latency are achieved. Also, the input and internal driving problems have been decreased, considerably. Because of similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be glitch-free. Furthermore, utilizing voltage full swing logics in these architectures has enhanced the speed of cascaded operations. The total latency and power dissipation of the proposed 5-2 compressor are about 302 ps and 248.62 μw, respectively, which is simulated by HSPICE using TSMC 0.18 μm CMOS technology.