FPGA implementation of hybrid fixed point - Floating point multiplication

This paper presents a hybrid fix point - floating point (FP) multiplication unit. It has as inputs a fixed point and a FP number and outputs a FP number. Algorithm and corresponding architecture are proposed. Two distinct approaches have been implemented on Xillinx Virtex 5 FPGA board: one geared towards performance whilst the second is optimized for cost. Synthesis results show an improvement up to 45% for slice LUT utilization for the cost optimized architecture and up to 35% less latency for the pro-performance implementation with respect to a composite unit made of a fixed to FP converter and a FP multiplier. Both proposed implementation require up to 50% less DSP blocks usage.