• DocumentCode
    637653
  • Title

    High input- and output-impedance functionality implementation in HV soi voltage buffers

  • Author

    Jankowski, Mariusz ; Napieralski, A.

  • Author_Institution
    Dept. of Microelectron. & Comput. Sci., Lodz Univ. of Technol., Lodz, Poland
  • fYear
    2013
  • fDate
    20-22 June 2013
  • Firstpage
    251
  • Lastpage
    254
  • Abstract
    This paper presents ways of enable and power-down functionality implementation in HV SoI buffers. Several HV buffer topologies are taken into account. Power-down, high input and output impedance functionality implementation approaches are presented and discussed.
  • Keywords
    buffer circuits; elemental semiconductors; network topology; power integrated circuits; silicon; silicon-on-insulator; HV SOI voltage buffer topology; Si; high input-impedance functionality; high-voltage integrated circuit; integrated circuit; output-impedance functionality; power-down functionality implementation; Impedance; Logic gates; Mirrors; Resistors; Switches; Topology; Transistors; High-voltage integrated circuits; SoI process; enable functionality; high impedance state;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference
  • Conference_Location
    Gdynia
  • Print_ISBN
    978-83-63578-00-8
  • Type

    conf

  • Filename
    6613351
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=637653