Tests of a readout front-end electronics for a pixel detector based on inverter amplifier

We report on the design and measurements of a prototype integrated circuit structure implemented in CMOS 180 nm technology and dedicated for readout of silicon pixel detectors. The prototype structure contains 16 channels, which are built of a charge sensitive amplifier and a main amplifier stage. We present both, the design procedure of the readout front-end electronics based on an inverter amplifier and the measurement results with the emphasis on the spread of analog parameters in the multichannel system. The single channel is characterized by: very low power dissipation level P_diss = 10.4 μW, equivalent noise charge at the main amplifier output ENC = 95 e^- rms at the peaking time t_p = 70 ns and detector capacitance C_DET = 100 fF. The charge sensitive amplifier and main amplifier stage have dimensions of 25 μm × 25 μm.