High performance FPGA-based implementation of a parallel multiplier-accumulator

This paper presents an FPGA-based design and implementation of a universal multiplier-accumulator unit. The proposed structure is based on an idea of parallel multiplication of properly aligned data stored in FPGA on-chip memory used as a cyclic buffer. The example application was implemented in Altera Cyclone II device and worked as a hardware accelerator of digital FIR filter. The results show that the higher performance for high-order FIR filter operation may be achieved in Altera Cyclone II family FPGAs in comparison to modern digital signal processors.