48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

Author

Shyng-Tsong Chen ; Tae-Soo Kim ; Seo-woo Nam ; Lafferty, Neal ; Chiew-Seng Koay ; Saulnier, Nicole ; Wenhui Wang ; Yongan Xu ; Duclaux, Benjamin ; Mignot, Yann ; Beard, Michael ; Yunpeng Yin ; Shobha, H. ; Van der Straten, Oscar ; Ming He ; Kelly, Jonatha

Author_Institution

IBM, Albany Nano-Technol. Center, Albany, NY, USA

fYear

2013

fDate

13-15 June 2013

Firstpage

1

Lastpage

3

Abstract

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.

Keywords

copper; integrated circuit interconnections; nanolithography; nanopatterning; Cu; Cu dual-damascene interconnects; SADP scheme; SIT technique; block lithography process; line level patterning; pitch interconnects build; pitch pattern; pitch split approach; self aligned double patterning scheme; sidewall image transfer technique; size 45 nm; size 48 nm; size 64 nm; smaller line pitch build; Bidirectional control; Dielectrics; Leakage currents; Lithography; Metals; Resistance; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2013 IEEE International

Conference_Location

Kyoto

Print_ISBN

978-1-4799-0438-9

Type

conf

DOI

10.1109/IITC.2013.6615589

Filename

6615589