CMOS 196 pico-second variable delay line incorporating active reflection-load in K-band

The monolithic variable delay line with the loss compensation is presented. The operation of the delay line relies on changing the impedance of two identical reflection-loads at the through and coupled ports of the directional coupler. The reflection-load is the composite network, consisting of a passive parallel resonator, and a frequency-selective negative resistor. The negative resistor maintains the quality factor of the resonator to reduce the variation on the insertion-loss of the delay line with different time delay. The circuit simulations and the on-wafer measurements based on the CMOS 0.13-μm 1P8M technology validate the proposed circuit. The maximum time delay of the prototype is 196.2 pico-seconds at 24 GHz. The insertion-loss is 1.53 dB at 24 GHz, and the loss-variation is less than 1.3 dB.