A passive quadrature generation scheme for integrated RF systems

This paper proposes a transformer-based quadrature generation scheme, which converts the RF input signal into the quadrature output signals. By employing multi-turn coil structure and new capacitive phase compensation on the through and coupling ports, the presented scheme can be implemented in a very compact footprint with high quality quadrature signal, making it feasible for cellular applications. Compared to conventional quadrature generation methods, this scheme provides low-loss, wide bandwidth, and most importantly robustness to process variations. As a proof-of-concept design example, we demonstrate a 2 GHz 8-turn transformer-based quadrature generation block implemented in a standard 65 nm CMOS process. The whole design only occupies 280 μm by 280 μm chip area. The detailed design parameters and the simulation results including quadrature balance, passive loss, input matching, and Monte-Carlo results under process variations are all presented.