Intricacies in digital CMOS implementation of a reconfigurable fuzzy logic traffic light controller

In this paper, the procedure of CMOS design of a reconfigurable fuzzy traffic light control that may work in a severe condition is discussed. The chip receives the membership degree parameters and traffic density indexes. The membership degree is allowed to have variable numbers of reconfigurable trapezoid patterns. Import/export of data is carried out through a serial link. The chip is designed using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) implementing an optimized fuzzy traffic controller developed in [1]. Based on the traffic density, the algorithm decides whether to terminate the current green phase or to extend it for some more time for better intersection traffic handling. Design is tested versus full software implementation of the algorithm. The result exhibits successful hardware implementation. Then, the layout of the chip based on minimum die area is also derived.