Title :
Identification algorithm implemented on a NOE-PWL ASIC
Author :
Lifschitz, O.D. ; Agamennoni, O. ; Julian, Pedro
Author_Institution :
Dept. de Ing. Electr. y de Computadoras, Univ. Nac. del Sur, Baha Bianca, Argentina
Abstract :
In this paper an Application Specific Integrated Circuit (ASIC) specially oriented to the implementation of an identification algorithm of a Nonlinear Output Error (NOE) model structure based on Piecewise Linear (PWL) basis functions is presented. The mathematical foundations for the identification process and the results from an (Field-Programmable Gate Array) FPGA implementation are described. The performance of the proposed ASIC is showed on an example.
Keywords :
application specific integrated circuits; field programmable gate arrays; piecewise linear techniques; FPGA implementation; NOE model structure; NOE-PWL ASIC; PWL basis functions; application specific integrated circuit; field-programmable gate array; identification algorithm; identification process; mathematical foundations; nonlinear output error model structure; piecewise linear basis functions; Educational institutions; IEEE catalog; NOE; PWL ASIC; Quantization errors;
Conference_Titel :
Micro-Nanoelectronics, Technology and Applications (EAMTA), 2013 7th Argentine School of
Conference_Location :
Buenos Aires
