A PWL ASIC design for maximum throughput

Author

Lifschitz, O.D. ; Julian, Pedro ; Agamennoni, O.

Author_Institution

Dept. de Ing. Electr. y de Computadoras, Univ. Nac. del Sur, Baha Bianca, Argentina

fYear

2013

fDate

15-16 Aug. 2013

Firstpage

92

Lastpage

95

Abstract

This paper presents the design of a digital architecture for a Simplicial piecewise-linear (PWL) integrated circuit (IC). This design maximizes the IC throughput by using a enhance pipeline architecture and taking advantage of the maximum memory device performance. The system latency is also minimized in order to allow feedback implementations at maximum output speed. Simulations and experimental results on a Field Programmable Gate Array (FPGA) implementation are included to showed the achieved performance.

Keywords

application specific integrated circuits; field programmable gate arrays; integrated circuit design; integrated circuit reliability; FPGA implementation; PWL ASIC design; digital architecture; feedback implementations; field programmable gate array; maximum memory device performance; maximum output speed; maximum throughput; pipeline architecture enhancement; simplicial piecewise-linear integrated circuit; system latency; Educational institutions; IEEE catalog; Digital architecture; NOE; PWL;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro-Nanoelectronics, Technology and Applications (EAMTA), 2013 7th Argentine School of

Conference_Location

Buenos Aires

Type

conf

Filename

6621084