Modelling and implementation of an accumulator-based ADPLL on a Virtex-5

In this work, we describe the implementation of an accumulator-based ADPLL on a Virtex 5. The ADPLL includes a Time-to-Digital Converter (TDC) that is based on two delay-lines and an oscillator. The resolution of the TDC is 1ns. The Digitally-Controlled-Oscillator (DCO) in the ADPPLL is implemented with a fixed-frequency oscillator and a digitally-controlled frequency divider. The period of the DCO can be set with a precision of 5ns. A digital filter based on finite difference equations is included in the ADPLL. Equation-based models are reported for all the building-blocks of the ADPLL. Simulated and measured step responses of the PLL are compared.