Modelling and implementation of an accumulator-based ADPLL on a Virtex-5

Author

Brandonisio, F. ; Melinn, D. ; Kennedy, Michael Peter ; Guerra, Danielle ; Deviato, M. ; Napoli, E.

Author_Institution

Dept. of Electron., Univ. Coll. Cork, Cork, Ireland

fYear

2012

fDate

28-29 June 2012

Firstpage

1

Lastpage

6

Abstract

In this work, we describe the implementation of an accumulator-based ADPLL on a Virtex 5. The ADPLL includes a Time-to-Digital Converter (TDC) that is based on two delay-lines and an oscillator. The resolution of the TDC is 1ns. The Digitally-Controlled-Oscillator (DCO) in the ADPPLL is implemented with a fixed-frequency oscillator and a digitally-controlled frequency divider. The period of the DCO can be set with a precision of 5ns. A digital filter based on finite difference equations is included in the ADPLL. Equation-based models are reported for all the building-blocks of the ADPLL. Simulated and measured step responses of the PLL are compared.

Keywords

digital filters; finite difference methods; frequency dividers; oscillators; phase locked loops; ADPLL; DCO; TDC; Virtex-5; accumulator; delay-line; digital filter; digitally-controlled frequency divider; digitally-controlled-oscillator; finite difference equation; fixed-frequency oscillator; time-to-digital converter; All-Digital PLL; FPGA; Time-to-Digital Converter; Virtex;

fLanguage

English

Publisher

iet

Conference_Titel

Signals and Systems Conference (ISSC 2012), IET Irish

Conference_Location

Maynooth

Electronic_ISBN

978-1-84919-613-0

Type

conf

DOI

10.1049/ic.2012.0175

Filename

6621154