UML state machine implementation in FPGA devices by means of dual model and Verilog

The paper presents the methodology of the logic controller development process based on the UML state machine diagram. The development process covers the logic synthesis and the implementation by means of the intermediate model based on Petri net formalism. The transformation between these two formal models is performed at the metamodels level according to the Model Driven Architecture (MDA). Semantics of the hierarchical configurable Petri net (HCfgPN) was adopted for the preemption and resumption mechanism. Operational subnet of HCfgPN model may be verified using formal methods.