Design of variable latency adder based on present and transitional states prediction

A novel circuit architecture for variable latency adder based on present and transitional states prediction (PTSP) method is presented in this paper, for taking the low power benefits of voltage-over-scaling. With the scaling down of CMOS technology, failure from process variation and high power consumption has become severe problem in VLSI design and the traditional conservative methodology is about to reach its limit. The technique of adaptive clocking has been proved promising to jointly address the mentioned two issues above. Previous works have focused on two or multi-stage predictions of present input data with error recovery but ignored the data correlation, which could result plenty of redundant cycles. In this work, along with the present data, sequence dependence between successive data is also introduced into function speculation and realized by a simple feedback strategy. Analytical energy saving and performance models have been deduced and validated by simulation using Hspice with 65nm CMOS technology, where the redundant cycles are eliminated up to 16% and the maximum energy saving is 15% with 3% area overhead, being compared with conventional adaptive clocking adder. Furthermore, the new adder with PTSP is applied to the domain of approximate computation and gets a decrement in error deviation of up to 50% in an accumulator.