DocumentCode
642616
Title
Evaluation of hop count advantages of network-coded 2D-mesh NoCs
Author
Vonbun, Michael ; Wallentowitz, Stefan ; Feilen, Michael ; Stechele, Walter ; Herkersdorf, Andreas
Author_Institution
Inst. for Integrated Syst., Tech. Univ. Munchen, Munich, Germany
fYear
2013
fDate
9-11 Sept. 2013
Firstpage
134
Lastpage
141
Abstract
Network-on-Chip (NoC) have become favorable for on-chip communication, especially with the ever rising number of communication partners in future manycore system-on-chip. NoCs that are based on mesh topologies with dimension-routing are well-established as they scale well with the increasing number of communication partners and allow efficient router design. To be able to serve application demands with efficiency, sophisticated features such as multicasting become an increasingly important factor in future NoC-based systems. The 2D-mesh/dimension-routing combination, however, suffers from performance degradation especially in the case of multicast communication as the network infrastructure is utilized suboptimally. Approaching this problem, we investigate the potential of network-coded Network-on-Chip (ncNoC) compared to classical 2D-mesh/dimension-routing NoCs. We adapt a high level evaluation method to compute the minimum hop count equivalent using network coding which enables us to compare network-coded and dimension-routed hop count cost. Within this environment we can demonstrate the full potential of network coding for both the butterfly and generalized multicast connection settings. We can show that network coding is never outperformed by dimension-routing in terms of required hop counts and, more important, identify multi-source scenarios with only a limited number of sinks per source to be the most advantageous connection settings for coded NoCs.
Keywords
multicast communication; network topology; network-on-chip; 2D-mesh-dimension-routing combination; hop count advantages; mesh topology; multicast communication; multicast connection settings; multisource scenarios; network-coded 2D-mesh NoC; network-on-chip; on-chip communication; Network coding; Network topology; Nickel; Routing; System-on-chip; Throughput; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on
Conference_Location
Karlsruhe
Type
conf
DOI
10.1109/PATMOS.2013.6662166
Filename
6662166
Link To Document