Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis

Static Random Access Memory (SRAM) has been under its under rebuilding stage in nanoscale era, pioneer aiming to rebuff the increased process variation and Short Channel Effects (SCE). In this paper, FinFET 10T process tolerant differential access and ultra low voltage operation SRAM cell topology is proposed. Back-gate biasing is used to manipulate gate work-function to extract variation aware and low power design. Built-in feedback mechanism is employed to achieve variation tolerant design during read operation. Monte-Carlo simulations for 5000 points with 3σ equivalent to 10% deviation from mean value are executed to quantify the effectiveness of proposed cell. Compare with a standard 6T Cell, we obtain 4.7× and 1.9× improvement in RNM and SNM, respectively, with a 3.5% reduction in WM. Moreover, RNM and WM are augmented by 6.5% and 3.6%, respectively, against PPN10T cell.