Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology

Modern heterogeneous multi-processor systems on chip (MPSoCs) require energy efficient network-on-chip (NoC) communication fabrics with high throughput. In [1] a high speed serial on-chip transceiver has been proposed, which is presented in this demonstration. Data is serialized to rates up to 10GBit/s per lane and transmitted differentially with low voltage swing of <; 200mV in the upper metal layers of the chip. Without the need of active buffer insertion link distances up to 6mm can be achieved. As shown in Fig. 1 the link features a source synchronous clocking architecture where a clock lane is shared among 9 data lanes for a total link data rate of 90GBit/s. The clock is completely stoppable, where a clock edge is only transmitted if there is a corresponding data bit. This enables low power consumption in idle periods of the link. The circuit is realized in 65nm LP CMOS technology. As shown in Fig. 2 an energy efficiency of 173fJ/bit/mm is achieved at 90GBit/s from 1.25V supply. The link allows for scaling of data rate and supply voltage to achieve optimized energy efficiency for given system constraints. As example, when running at 45GBit/s from 0.9V supply it consumes only 93fJ/bit/mm. At these operating points error free operation with bit error rate BER <; 10^-12 is achieved.