Implementation of a pulse-holding Time-to-Digital Converter on an FPGA

In this work, we describe the implementation of a pulse-holding Time-to-Digital Converter (TDC) on a Xilinx Spartan 6 FPGA. We describe the operation of a pulse-holding TDC and we compare it with that of a pulse-shrinking TDC, which is the most similar TDC in the literature. We then illustrate a Simulink model of a pulse-holding TDC and the TDC that was implemented on a FPGA. The pulse-holding TDC uses a moving average filter to remove the quantization noise and improve the precision of the measurements. We show from simulations and experiments that the maximum modulus of the difference between the the input and output of the TDC can be reduced from 2 ns to less than 70 ps by means of a moving average filter.