DocumentCode
642724
Title
Spatial computing architecture using randomness of memory cell stability under voltage control
Author
Yoshimura, C. ; Yamaoka, Masanao ; Aoki, Hidetaka ; Mizuno, Hidenori
Author_Institution
Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan
fYear
2013
fDate
8-12 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
A new computing architecture based on a ground-state search of the Ising model and the probabilistic behavior of a memory cell is proposed. To improve computer performance, a spatial computing architecture that defines an Ising model as the interface between software and hardware is proposed. Various problems can be represented as a spatial parameter in the Ising model. A memory-cell-array-based hardware is utilized to search for the ground state of the Ising model. The interaction between memory cells produces a state transition to lower energy, and the randomness of memory-cell stability at lower voltage helps escape from a local minimum. It was verified by simulation that the proposed architecture can solve practical problems such as factorization and the traveling-salesman problem.
Keywords
circuit stability; integrated circuit modelling; memory architecture; probability; storage management chips; voltage control; Ising model; ground-state search; local minimum; memory cell probabilistic behavior; memory cell stability randomness; memory-cell-array-based hardware; spatial computing architecture; state transition; traveling-salesman problem; voltage control; Bit error rate; Computational modeling; Computer architecture; Hardware; Microprocessors; Parallel processing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design (ECCTD), 2013 European Conference on
Conference_Location
Dresden
Type
conf
DOI
10.1109/ECCTD.2013.6662276
Filename
6662276
Link To Document