Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops

In this paper the results obtained by performing the Periodic Noise (PNoise) analysis of a Phase-Locked Loop (pll) modeled as a mixed analog/digital circuit are compared with those from experimental measurements. The PNoise analysis of this class of circuits is done by considering them as hybrid dynamical systems. Since the circuit simulators available on the academic and industrial shelves are not able to carry out this kind of simulation, experimental validation is mandatory to support numerical results and enforce the reliability of the proposed approach. A significant improvement of the PNoise analysis efficiency, in terms of reducing its computational burden when simulating noise in PLLs with a large frequency ratio, is also presented, which allows to more easily manage noise folding.