An LDO using stacked transistors on 65 nm CMOS

This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two pass transistors. The first pass transistor is controlled by the main error amplifier; the 2nd pass transistor is controlled by 2nd amplifier adjusting the division of the voltages between the two pass transistors. The paper presents circuit design and simulations results of a LDO with 500 mA output current using the 2.5 V transistors of the TSMC 65 nm CMOS low-power process technology.