DocumentCode
642758
Title
Lithography-aware 1-dimensional cell generation
Author
Po-Hsun Wu ; Lin, Mark Po-Hung ; Tung-Chieh Chen ; Tsung-Yi Ho ; Yu-Chuan Chen
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2013
fDate
8-12 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.
Keywords
CMOS integrated circuits; photolithography; 1D cell area; 1D design style; diffusion gaps; lithography-aware 1-dimensional cell generation algorithm; next generation CMOS technology; process technology; routing tracks; Algorithm design and analysis; CMOS integrated circuits; Integrated circuit interconnections; Layout; MOSFET; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design (ECCTD), 2013 European Conference on
Conference_Location
Dresden
Type
conf
DOI
10.1109/ECCTD.2013.6662310
Filename
6662310
Link To Document