Optimized frequency compensation topology for low-power three-stage OTAs

A power-efficient frequency compensation topology for three-stage transconductance amplifiers is presented in this paper. Stability analysis and design equations are carried out based on the small-signal model. Unlike many recently reported solutions, the proposed architecture do not rely upon parasitic and/or pole-zero cancellation, thus providing a more robust design. As an example, the proposed technique was used to design a three-stage amplifier in a standard CMOS 65-nm technology. The amplifier achieves a 2-MHz gain-bandwidth product when driving a 1-nF capacitance by consuming only 82 μW from a 2.5-V supply. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over previously reported solutions.