From software to accelerators with LegUp high-level synthesis

Author

Canis, Andrew ; Jongsok Choi ; Fort, Blair ; Ruolong Lian ; Qijing Huang ; Calagar, Nazanin ; Gort, M. ; Jia Jun Qin ; Aldham, Mark ; Czajkowski, Tomasz ; Brown, Shannon ; Anderson, Jon

Author_Institution

ECE Dept., Univ. of Toronto, Toronto, ON, Canada

fYear

2013

fDate

Sept. 29 2013-Oct. 4 2013

Firstpage

1

Lastpage

9

Abstract

Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.

Keywords

coprocessors; data visualisation; embedded systems; field programmable gate arrays; hardware-software codesign; program debugging; public domain software; software tools; FPGA; LegUp design methodology; LegUp high-level synthesis; OpenMP support; Pthreads; automatically-generated software/hardware coprocessor system; custom hardware accelerators; debugging support; dedicated hardware accelerators; embedded application; embedded system designers; energy benefits; hardware accelerator design process; hardware accelerator quality improvements; hardware partitioning; open-source high-level synthesis framework; performance benefits; software partitioning; system architecture; visualization tools; Clocks; Field programmable gate arrays; Hardware; Optimization; Pipeline processing; Radiation detectors; Software; FPGA; Hardware Accelerators; High Level Synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013 International Conference on

Conference_Location

Montreal, QC

Type

conf

DOI

10.1109/CASES.2013.6662524

Filename

6662524