Evolutionary Computation Based Retiming for High Speed Digital Filters

In the present work, we consider high level synthesis as a problem of optimally mapping a Data Flow Graph [DFG] specification of digital filters on to FPGA architecture. This optimality is achieved using retiming based on evolutionary computation method. Many retiming methods proposed in the literature are heuristic and produce only one solution based on any chosen optimization criterion. However, for multi optimization problems like retiming, evolutionary approach can lead to satisfactory results as optimization can be performed for a specific criterion considering the required constraints. This paper provides a novel approach to retime the digital filters based on evolutionary computation with speed as the criterion and area as the constraint. Clock period and number of registers are considered as the optimization requirement in the present work. For any digital filter, the minimum possible clock period is calculated based on critical path and component delays in that path. Using evolutionary computation, multiple re-timed solutions are generated with high speed and different output register counts. Depending on the area constraint, user can choose the retiming solution with particular register counts. Here, initial parent population is randomly generated. From the combination of parents and offsprings, next generation is selected and tournament selection is used in the present work. It is also seen that the solutions can be obtained with lesser processing time for bigger circuits then the existing methods. This evolutionary computation based retiming algorithm gives a framework where optimization can be performed for speed with area as the constraint. An environment is designed which generates synthesizable HDL of the retimed filter which intern reduces design cycle time.