Enhanced reduction of ground bounce noise in low leakage CMOS multiplier with combinational MTCMOS circuit

Author

Verma, Bipin Kumar ; Singh, S.B. ; Akashe, Shyam

Author_Institution

ITM Univ., Gwalior, India

fYear

2013

fDate

26-28 Sept. 2013

Firstpage

1

Lastpage

5

Abstract

Multi-Threshold CMOS (MTCMOS) is one of the most used circuit techniques to reduce the leakage current in idle circuit. Ground bounce noise produced during transition mode (Sleep-to-Active) is an important challenge in MTCMOS. In this paper we have designed our multiplier with different MTCMOS techniques to reduce the ground bounce noise and leakage current. The dependence of ground bounce noise on voltage scaling, transistor size and temperature is characterized with different MTCMOS circuit technique. The techniques are reduced ground bounce noise up-to 93% and standby leakage current up-to 99% respectively. It also reduces the active power by 53% respectively. Simulation results of multiplier have been performed on EDA tools with 45nm technology.

Keywords

CMOS logic circuits; combinational circuits; electronic design automation; integrated circuit noise; leakage currents; logic design; multiplying circuits; EDA tools; combinational MTCMOS circuit; electronic design automation; ground bounce noise reduction; leakage current; low leakage CMOS multiplier; multi-threshold CMOS; size 45 nm; transition mode; CMOS integrated circuits; Land surface temperature; Leakage currents; Noise; Switching circuits; Transistors; Very large scale integration; Ground Bounce Noise; Leakage Current; MTCMOS; Multiplier; mode transition;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Computing and Control (ISPCC), 2013 IEEE International Conference on

Conference_Location

Solan

Print_ISBN

978-1-4673-6188-0

Type

conf

DOI

10.1109/ISPCC.2013.6663441

Filename

6663441