Clock distribution networks — A case study using multi VDD and multi threshold level converters

Clock Distribution has played a key role in designing the synchronous systems. Even with the systems moving towards Globally Asynchronous and Locally Synchronous (GALS) a need for low power clock distribution network exists as it consumes a major portion of the circuit power. In this paper we demonstrate the effect of various level converters on clock distribution networks. Also we propose a novel low to high level converter which performs better for asynchronous latch based logic circuits at relatively higher frequency where the existing level converters fail. The simulation work was carried out using Cadence Virtuoso Schematic Composer at the frequencies of 10 MHz, 100 MHz, 200 MHz, 250 MHz, 400 MHz and 500 MHz. The proposed circuit performs better in terms of level retention at higher frequencies and power consumption when intermediate frequencies are considered.