Title :
System level hardware testing of a high speed MAP decoder implemented on FPGA
Author :
Shrestha, Ranjay ; Paily, Roy
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
Abstract :
In this paper, a systematic approach of hardware prototyping and testing a digital design of maximum-a-posteriori (MAP) decoder for a communication system is presented. A MAP decoder architecture for the high speed application is chosen for the implementation on field-programmable-gate-array (FPGA) board. The test-setup of a communication system with binary-phase-shift-keying (BPSK) modulation scheme in an additive-white-Gaussian-noise (AWGN) channel environment is designed to verify the hardware prototype of the decoder. Subsequently, the integration of hardware prototype with integrated logic analyzer core using control cores and parallel cables are presented. The hardware prototype of MAP decoder implemented on FPGA has achieved a biterror-rate (BER) of 10-4 at an Eb/N0 of 4.75 dB and has a degraded performance as compared to simulated MAP algorithm by approximately 0.2 dB. In addition, the implemented MAP decoder has a maximum achievable frequency of 411 MHz.
Keywords :
AWGN channels; error statistics; field programmable gate arrays; maximum likelihood decoding; phase shift keying; AWGN channel; BER; BPSK; FPGA; additive white Gaussian noise channel; binary phase shift keying; bit error rate; control cores; field programmable gate array; frequency 411 MHz; high speed MAP decoder; integrated logic analyzer core; maximum-a-posteriori decoder; parallel cables; system level hardware testing; Bit error rate; Communication systems; Decoding; Field programmable gate arrays; Hardware; Measurement; BER performance; FPGA; MAP algorithm; communication system and VLSI system design;
Conference_Titel :
Signal Processing, Computing and Control (ISPCC), 2013 IEEE International Conference on
Conference_Location :
Solan
Print_ISBN :
978-1-4673-6188-0
DOI :
10.1109/ISPCC.2013.6663445
