DocumentCode :
643612
Title :
Two methods of design and implementation of ACELP vocoder
Author :
Yi Zhao ; Sheng Zhang ; Xiaokang Lin
Author_Institution :
Shenzhen Key Lab. of Inf. Sci. & Technol., Tsinghua Univ., Shenzhen, China
fYear :
2013
fDate :
5-8 Aug. 2013
Firstpage :
1
Lastpage :
6
Abstract :
ACELP is a type of voice coder algorithm that compresses speech signal based on model parameters of human voice. This paper presents two methods for design and implementation of ACELP vocoder. One is fully hardware design, it is characterized by pipelining and parallel operation of functional units, and it has been tested on an FPGA; the other is hardware-software co-design, it is characterized by dividing the algorithm into hardware part and software part, and it has been tested with NIOS II and FPGA. Experiments´ results show that fully hardware implementation can achieve faster speed and smaller latency, and co-design owns shorter design cycle and better voice quality.
Keywords :
field programmable gate arrays; hardware-software codesign; logic design; speech coding; vocoders; ACELP vocoder; FPGA; hardware design; hardware-software codesign; speech signal compression; voice coder algorithm; Algorithm design and analysis; Decoding; Field programmable gate arrays; Hardware; Software; Software algorithms; Speech; ACELP; FPGA; NIOS II; fully hardware design; hardware-software co-design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing, Communication and Computing (ICSPCC), 2013 IEEE International Conference on
Conference_Location :
KunMing
Type :
conf
DOI :
10.1109/ICSPCC.2013.6663884
Filename :
6663884
Link To Document :
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