DocumentCode
644299
Title
Optimal networks from error correcting codes
Author
Tomic, Ratko V.
Author_Institution
Infinetics Technologies, Inc., 37 Chelsea Street, Boston, MA 02129, USA
fYear
2013
fDate
21-22 Oct. 2013
Firstpage
169
Lastpage
179
Abstract
To address growth challenges facing large Data Centers and supercomputing clusters a new construction is presented for scalable, high throughput, low latency networks. The resulting networks require 1.5–5 times fewer switches, 2–6 times fewer cables, have 1.2–2 times lower latency and correspondingly lower congestion and packet losses than the best present or proposed networks providing the same number of ports at the same total bisection. These advantage ratios increase with network size.
Keywords
Eigenvalues and eigenfunctions; Error correction codes; Generators; Network topology; Symmetric matrices; Topology; Vectors; Data center; Ethernet; HPC; InfiniBand; bisection; error correcting codes; integrated control plane; network topology; topology optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Architectures for Networking and Communications Systems (ANCS), 2013 ACM/IEEE Symposium on
Conference_Location
San Jose, CA, USA
Print_ISBN
978-1-4799-1640-5
Type
conf
DOI
10.1109/ANCS.2013.6665199
Filename
6665199
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