Generation of a multilevel SPWM technique of 3, 9 and 21 levels with FPGAs

Author

Salgado-Herrera, N.M. ; Medina-Rios, Aurelio ; Ramos-Paz, Antonio ; Rodriguez-Rodriguez, J.R.

Author_Institution

Div. de Estudios de Posgrado in Morelia, Univ. Michoacana de San Nicolas de Hidalgo, Morelia, Mexico

fYear

2013

fDate

22-24 Sept. 2013

Firstpage

1

Lastpage

5

Abstract

This paper deals with the implementation of parallel processing SPWM multilevel techniques through programmable gate arrays (Field Programmable Gate Arrays, FPGAs). It is shown that switching losses in power converters significantly decreases with an increased number of levels in the SPWM signal, thus providing an efficient energy transfer. The multilevel SPWM control response of 3, 9 and 21 levels in VHDL through the FPGA Xilinx Spartan family is illustrated.

Keywords

PWM power convertors; field programmable gate arrays; hardware description languages; FPGA; VHDL; Xilinx Spartan; efficient energy transfer; field programmable gate arrays; multilevel SPWM technique generation; parallel processing SPWM multilevel techniques; power converters; switching losses; Field programmable gate arrays; Frequency modulation; Inverters; Parallel processing; Power harmonic filters; Pulse width modulation; FPGA; granularity; multilevel-SPWM; parallel processing; power systems;

fLanguage

English

Publisher

ieee

Conference_Titel

North American Power Symposium (NAPS), 2013

Conference_Location

Manhattan, KS

Type

conf

DOI

10.1109/NAPS.2013.6666843

Filename

6666843