Title :
Instruction set extensions for photonic synchronous coalesced accesses
Author :
Keltcher, Paul ; Whelihan, David ; Hughes, John
Author_Institution :
Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA, USA
Abstract :
Microprocessors have evolved over the last forty-plus years from purely sequential single operation machines, to pipelined super-scalar, to threaded and SIMD, and finally to multi-core and massive multi-core/thread machines. Despite these advances, the conceptual model programmers use to program them is still that of a single threaded register file bound math unit that can only be loosely synchronized with other such processors. This lack of explicit synchrony, caused by limitations of metal interconnect, limits parallel efficiency. Recent advances in silicon photonic-enabled architectures [1, 5, 7] promise to greatly enable high synchrony over long distances (centimeters or more). In this paper, it is shown that global synchrony changes the way computers can be programmed by introducing a new class of ISA level instruction: the globally-synchronous load-store. In the context of multiple load-store machines, the globally synchronous load-store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. This operation is described, and its ISA implications explored in the context of the distributed matrix transpose, which exhibits a high degree of data non-locality, and is difficult to efficiently parallelize on modern architectures.
Keywords :
computer architecture; instruction sets; shared memory systems; ISA level instruction; distributed matrix transpose; global synchrony; globally synchronous load-store architecture; independent load-store machines; instruction set extensions; multiple load-store machines; photonic synchronous coalesced accesses; single load-store machine; Graphics processing units; Instruction sets; Memory management; Photonics; Transmission line matrix methods; coalesced memory; computer architectures; instruction set; photonics; shared memory;
Conference_Titel :
High Performance Extreme Computing Conference (HPEC), 2013 IEEE
Conference_Location :
Waltham, MA
Print_ISBN :
978-1-4799-1364-0
DOI :
10.1109/HPEC.2013.6670326