Investigation of the ESD induced clock disturbances in portable electronic products

ESD events can induce noise on the system clock which may lead to soft-errors in the portable electronic products. This paper presents measurement techniques to investigate the ESD induced clock disturbances. At first, the soft-errors due to system level ESD testing on a DUT are shown. Next, local field scanning and direct injection are performed to identify ESD sensitive areas/traces. Techniques for soft-error threshold measurement using synchronized noise injection techniques are shown. Short time FFT (STFFT) based spectrogram method to investigate the PLL output frequency deviation due to the clock line noise, is presented.