• DocumentCode
    646965
  • Title

    Keynote talk II: Designing tomorrow´s chips

  • Author

    Hoskote, Yatin

  • fYear
    2013
  • fDate
    18-20 Oct. 2013
  • Firstpage
    75
  • Lastpage
    76
  • Abstract
    Next generation systems in such domains as wearables and Internet of Things will have capabilities for sensing, recognition and intelligence. Such systems integrate multiple hardware components - including sensors, actuators, compute and commumcations modules - together with complex software in an ultra-low power envelope. This talk will explore the needs of a design environment that is required to rapidly design such systems. A top down model-based design methodology that follows a refinement based approach will leverage such a design environment. Many of the pieces exist today at various levels of maturity, but there remain gaps that need to be addressed.
  • Keywords
    Internet of Things; actuators; integrated circuit design; next generation networks; sensors; Internet of Things; actuators; chip design; communications modules; complex software; design environment; multiple hardware components; next generation systems; refinement-based approach; sensors; top down model-based design methodology; ultralow power envelope; Awards activities; Chip scale packaging; Computers; IP networks; Next generation networking; Sensors; System-on-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign (MEMOCODE), 2013 Eleventh IEEE/ACM International Conference on
  • Conference_Location
    Portland, OR
  • Print_ISBN
    978-1-4799-0903-2
  • Type

    conf

  • Filename
    6670943