DocumentCode :
647280
Title :
Hybrid logarithmic number system arithmetic unit: A review
Author :
Ismail, R.C. ; Zakaria, M.K. ; Murad, S.A.Z.
Author_Institution :
Sch. of Microelectron. Eng., Univ. Malaysia Perlis, Kangar, Malaysia
fYear :
2013
fDate :
18-19 Sept. 2013
Firstpage :
55
Lastpage :
58
Abstract :
Logarithmic number system (LNS) arithmetic has the advantages of high performance and high-precision in complex function computation. However, the large hardware problem in LNS addition/subtraction computation has made the large word-length LNS arithmetic implementation impractical. In this paper, the concept of merging the LNS and Floating Point (FLP) operation into a single arithmetic logic unit (ALU) that can execute addition/subtraction and division/multiplication more faster, precise and less complicated has been reviewed. The advantages of using hybrid system were highlighted while comparing and explaining about FLP and LNS.
Keywords :
floating point arithmetic; logic design; ALU; FLP operation; LNS addition-subtraction computation; LNS arithmetic; arithmetic logic unit; floating point; hybrid logarithmic number system arithmetic unit; arithmetic logic unit; floating point; hybrid; logarithmic number system;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ICCAS), 2013 IEEE International Conference on
Conference_Location :
Kuala Lumpur
Type :
conf
DOI :
10.1109/CircuitsAndSystems.2013.6671617
Filename :
6671617
Link To Document :
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