Optimized rate matching architecture for a LTE-Advanced FPGA-based PHY

In this paper we present an optimized rate matching architecture for a LTE-Advanced FPGA-based physical layer. Since LTE-Advanced can reach up to rates of 1 Gbps in downlink, and since rate matching is in that critical path, it is very important that the design of the hardware architecture be efficient enough to allow this high data rate with little resources as possible. If not well planned, implementations on FPGAs can be quite challenging, limiting the choices of speed grades and FPGAs sizes capable of supporting such requirements. We propose efficient hardware architecture for the LTE-Advanced rate matching generic procedure; occupying only 218 slices and 9 block RAMs and performing in frequencies greater than 400 MHz in a FPGA-based solution.