DocumentCode
648532
Title
Noise effect estimation and reduction in high-speed voltage controlled oscillators
Author
Melikyan, Vazgen ; Balabanyan, Abraham ; Durgaryan, Armen
Author_Institution
Synopsys Armenia CJSC, Yerevan, Armenia
fYear
2013
fDate
27-30 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
The paper presents an investigations of various noise effects on frequency stability of differential ring voltage controlled oscillators. The impact of bias generator parameters and PVT variations on noise immunity is demonstrated and simplified models are developed. A method of bias generator parameter calculation and PVT compensation is suggested. The efficiency of the developed means is tested on a deep submicron CMOS phase locked loop.
Keywords
circuit noise; phase locked loops; phase locked oscillators; PVT compensation; PVT variations; bias generator parameters; complimentary metal oxide semiconductors; deep submicron CMOS phase locked loop; differential ring voltage controlled oscillators; frequency stability; high-speed voltage controlled oscillators; noise effect estimation; noise effect reduction; noise immunity; process-voltage-temperature variations; PLL; PVT; SSN; VCO; Voltage controlled oscillator; jitter; supply noise; thermal noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium, 2013 East-West
Conference_Location
Rostov-on-Don
Print_ISBN
978-1-4799-2095-2
Type
conf
DOI
10.1109/EWDTS.2013.6673117
Filename
6673117
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