Fault-injection testing: FIT-ability, optimal procedure and tool for FPGA-based systems SIL certification

Author

Kharchenko, V. ; Sklyar, Volodymyr ; Odarushchenko, Oleg ; Ivasuyk, A.

Author_Institution

Nat. Aerosp. Univ. named after N.E. Zhukovsky “KhAI”, Kharkiv, Ukraine

fYear

2013

fDate

27-30 Sept. 2013

Firstpage

1

Lastpage

5

Abstract

Challenges related to verification and validation (VV) of FPGA-based safety critical I&C systems (FICS) are analyzed. One of the mandatory techniques applied in process of VV and certification to requirements of IEC 61508 according with safety integrity level (SIL) is the fault insertion or injection testing (FIT). Specific features of FICS SIL-certification and FIT are described. Concept of FIT-ability, some theoretical issues and algorithm of the optimal FIT procedure taking into account different points and means of fault injection are suggested. The developed technique and tool VTP has been applied to verify modules of FPGA-based platform RadICS during SIL-certification.

Keywords

IEC standards; certification; computerised instrumentation; electrical safety; fault diagnosis; field programmable gate arrays; formal verification; safety-critical software; FICS; FIT; FPGA-based safety critical I&C system; FPGA-based system SIL certification; IEC 61508; RadICS; SIL certification; VTP; VV technique; fault injection testing; safety integrity level; verification and validation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Test Symposium, 2013 East-West

Conference_Location

Rostov-on-Don

Print_ISBN

978-1-4799-2095-2

Type

conf

DOI

10.1109/EWDTS.2013.6673129

Filename

6673129