DocumentCode :
648548
Title :
On the problem of selection of code with summation for combinational circuit test organization
Author :
Efanov, Dmitry ; Sapozhnikov, Vladimir ; Sapozhnikov, Vladimir ; Blyudov, Anton
Author_Institution :
Autom. & Remote Control on Railways Dept., Petersburg State Transp. Univ., St. Petersburg, Russia
fYear :
2013
fDate :
27-30 Sept. 2013
Firstpage :
1
Lastpage :
6
Abstract :
In this paper authors adduce results of the research in the theory of synthesis of concurrent error detection (CED) circuits based on use of codes with summation. New codes with summation are obtained and their properties of errors among data bits detection are determined. The complete classification of codes with summation is adduced.
Keywords :
codes; combinational circuits; integrated circuit testing; CED circuits; code selection; combinational circuit test organization; concurrent error detection circuits; data bits detection; summation; synthesis theory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
Type :
conf
DOI :
10.1109/EWDTS.2013.6673133
Filename :
6673133
Link To Document :
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