Title :
Coupled TCAD-SPICE simulation of parasitic BJT effect on SOI CMOS SRAM SEU
Author :
Petrosyants, K.O. ; Kharitonov, I.A. ; Popov, D.A.
Author_Institution :
Moscow Inst. of Electron. & Math., Nat. Res. Univ. “Higher Sch. of Econ.”, Moscow, Russia
Abstract :
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65 nm are presented.
Keywords :
CMOS memory circuits; SPICE; SRAM chips; bipolar transistors; radiation hardening (electronics); technology CAD (electronics); SOI CMOS SRAM SEU; SOI CMOS SRAM cells; coupled TCAD-SPICE simulation; mixed-mode approach; parasitic BJT effect; particle strike position; single event upsets; size 0.25 nm to 65 mum; two-dimensional semiconductor device simulation;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673141
