Implementation of address-based data sorting on different FPGA platforms

Among numerous tasks that need to be solved, sorting is considered to be one of the most important. Since it is time consuming for large volumes of data, acceleration is greatly required for many practical applications. It is also important to discover such methods that take advantage of the implementation platform (due to its uniqueness) and consider not only the number of the required operations, but also efficiency of their implementation in hardware circuits. This paper evaluates implementations of address-based data sorting algorithms in field-programmable gate array (FPGA) circuits. It is demonstrated that the proposed technique can be used efficiently both in low cost FPGAs as well as in advanced FPGAs, and the number of sorted items (with sizes of up to 32 bits) can reach 2³².