Title :
Power reduction of 7T dual-Vt SRAM cell using forward body biasing
Author :
Jahromi, Sahba Sabetghadam ; Bounik, Raziyeh
Abstract :
A low power seven transistors (7T) dual threshold voltage (dual-Vt) SRAM cell in 65nm CMOS technology is presented. Using the conventional dual-Vt 7T structure, reduces both read/write and standby (leakage) power consumption significantly compared to the conventional 6T SRAM cell. In order to reduce the leakage power consumption even further, a forward body biasing (FBB) technique was used for the stacked read transistors. This optimization resulted in significant reduction in standby and a slight reduction in write power dissipation.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; power consumption; CMOS technology; forward body biasing; leakage power consumption; low power seven transistors dual threshold voltage SRAM cell; power reduction; read/write; size 65 nm; stacked read transistors; standby power consumption; write power dissipation;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673220
