Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering

Reverse engineering is a great peril for hardware security especially when functional behavior extraction of the circuit is needed. In this paper a novel method is presented to obfuscate the wiring topology of the design for hindering or even preventing the reverse engineering. In the proposed methodology, new standard cells (Wire Scrambling cells) are presented and then, a physical design methodology is proposed in which wiring topology of the circuit is scrambled automatically using the suggested wire scrambling cells. Experimental results show that reverse engineering can be hindered or even practically protected in cost of negligible overheads in area, power consumption and total wire length.